A phase locked loop can be considered as a feedback loop control system which closely tracks a reference clock input. A typical PLL structure is shown in FIG. 1. As can been in the figure the difference between a reference clock and digitally controlled oscillator (DCO) is fed to a loop filter, which is basically a proportional/integral (PI) controller. The output of the loop filter then is used to steer the output phase of the DCO such that it closely tracks the reference clock input phase.
The loop filter parameters (P and I) are designed to meet certain performance requirements, such as band-width, initial locking time, dynamic tracking etc. For example, when the input reference clock is contaminated with jitter and wander, the filter bandwidth is set to minimize the effect of jitter or wander on the reference input. Lowering the loop filter bandwidth to improve wander and jitter elimination will have a adverse effect on how fast PLL can track reference input signal. In practice, a trade-off is required between tracking the input phase and rejecting wander and jitter.
Recently there has been much interest in clock synchronization over packet networks, where, as shown in FIG. 2, reference clock phase information is transmitted through dedicated timing packets by a server over a packet switched network (PSN). At the other end of the network, a client synchronizes its clock with the server using the timing packets. This method can be used to synchronize systems that are connected through a packet network, such as wireless basestations.
One of the main challenges in this synchronization approach is that the timing packets are most likely subjected to packet delay variations (PDV) inherent in any packet switched network. As a result, at the client side, depending on the packet delay variations, the recovered reference clock will have a high level of jitter and wander, which for most applications will not be acceptable.
A traditional PLL system is not able to remove jitter and wander in this case because the simple loop filter in a traditional PLL cannot handle a high level of jitter and wander. To be able to remove substantial amounts of wander, the loop filter should be set to very low frequencies. This requires the use of very stable local oscillators at the server or at the client side, which may not be cost effective or practical.
Also, the network PDV has a non-stationary nature, which results in rapid or slow movement of recovered phase at the client side. Traditional PLLs are not designed to handle non-stationary noise.
In addition, systems for timing recovery over packets networks are time varying in nature. Traditional PLLs are designed for time-invariant systems and are not suited for this kind of application.
A PLL is single-input single-output system designed to lock its output phase to a single input clock reference and cannot directly be applied to the case when multiple timing packet streams are traceable to the same primary reference clock (PRC).
To be able to handle some of these shortcomings of the classic PLL for timing recovery over packet networks, the prior art suggests using a two stage scheme with the first stage being a packet filter which only selects timing packets that have least amount of packet delay variations and the second stage being normal PLL such as the one shown in FIG. 1. The main problem with this approach is that the performance of the clock recovery algorithm relies greatly on the number of filtered timing packets. When there are very few or none of these so-called minimum delayed timing packets available, the algorithm may fail to recover or track the server clock. There are also other methods based, e.g., on averaging the timing packets but these methods also suffer from poor performance when dealing with larger packet delay variations.
None of the prior art offers an optimal scheme that can exploit the space diversity of packet networks when there are two or more timing packet streams.